1. Field of the Invention
The present invention relates to a multi-bit pipeline analog-to-digital converter (ADC) having a merged capacitor switching structure, and more particularly, to a technique that reduces the number of required capacitors by merging capacitors used in a multiplying digital-to-analog converter (MDAC) of a multi-bit pipeline ADC and can solve the problems of a demand for an additional reference voltage resulting from the merging of capacitors and a change in the input common mode voltage of an amplifier.
2. Discussion of Related Art
In order to process a video signal in an image system, a minute analog signal must be converted into a digital signal insusceptible to noise, which is performed by an ADC.
Video information output from a sensor is very delicate, thus requiring a high-resolution ADC capable of precisely distinguishing a signal. For a communication system and a video processing and application system, such as mobile communication, asynchronous digital subscriber line (ADSL), International mobile telecommunication (IMT)-2000, digital camcorders, high-definition televisions (HDTVs), etc., as well as an image system, a high-performance ADC having a high resolution of 12 bits to 14 bits and a high sampling rate of several tens of megahertz (MHz) is required.
Among well-known conventional ADC structures, flash, folding, subranging and pipeline structures can be used for high-speed signal processing. Recently, among these structures, a multi-bit pipeline structure optimizing speed, power consumption and area is frequently used to satisfy both conditions of high-speed processing and high resolution.
FIG. 1 is a circuit diagram of an MDAC of a conventional multi-bit pipeline ADC.
As illustrated in FIG. 1, a conventional N-bit MDAC using a unit capacitor has a switched-capacitor structure capable of adjusting an amplification factor according to the ratio of a feedback capacitor value and a sampled capacitor value. For such an amplifying operation, the conventional N-bit MDAC comprises 2N sampling capacitors C1 to C2N 10, two feedback capacitors CF1 and CF2 20, an amplifier 30, an N-bit flash ADC 40, a decoding circuit 50 for adjusting switches according to a digital code, and so on.
As shown in FIG. 1, the mismatch between capacitors limits the resolution by increasing the differential nonlinearity (DNL) of ADCs. A common centroid geometry layout technique generally improves the capacitor match. However, it is difficult to reduce random errors during fabrication.
In order to solve the problem, a merged capacitor switching structure in which two capacitors are merged into one capacitor has been suggested. As described below with reference to FIGS. 2A and 2B, however, in the conventional merged capacitor switching structure, an additional reference voltage is required, or the input common mode voltage of an amplifier is changed.
FIGS. 2A and 2B are circuit diagrams of conventional merged capacitor switching structures.
When the ratio of a sampling capacitor and a feedback capacitor is kept uniform, it is possible to have the same amplification factor as a previous MDAC. According to this, in FIG. 2A, a method is disclosed which reduces the number of required capacitors to the half by merging two feedback capacitors CF1 and CF2 into one CF1′ and also merging every two sampling capacitors C1 to C2N into one C′ to C2N−1′.
When the number of required capacitors is reduced by merging every two capacitors used in the MDAC into one, two codes generated from the decoding circuit 50 determine the amount of electric charge of the merged capacitors C1′ to C2N−1′. When the code is “00”, it may be simply connected to a reference voltage −VREF. And, when the code is “11”, it may be simply connected a reference voltage +VREF. However, when the code is “10” or “01”, an additional reference voltage, e.g., GND or VCML, is required because the amount of electric charge stored in the capacitors must be 0 upon generation of the code.
In order to solve such a problem of the additional reference voltage, in FIG. 2B, a method is disclosed which equalizes the amounts of electric charge stored in differential capacitors CA2′ and CB2′ by applying the same reference voltage +VREF or −VREF to the differential capacitors CA2′ and CB2′ to which the code “10” or “01” is applied.
According to the method, since the total amount of electric charge stored in the respective differential capacitors increases or decreases depending on a used reference voltage, the input common mode voltage of the amplifier 30 increases when connecting with the reference voltage +VREF or decreases when connecting with the reference voltage −VREF in comparison with a sampled input common mode voltage VCML. Therefore, the trans-conductance of the amplifier 30 varies according to the input digital code, thus increasing the settling time of an output signal.